The present invention is related to systems and methods for developing and testing semiconductor devices, and in particular to systems and methods for utilizing a group of efuses in a semiconductor device.
Electronic fuses are deployed in various semiconductor devices and allow a semiconductor manufacturer to perform one or more post production customizations of a given semiconductor device. Turning to FIG. 1, a known electronic fuse circuit 100 is depicted. Fuse circuit 100 includes a fuse 130 that is physically connected to a fuse transistor 110. In addition, the output of fuse 130 is physically connected to the input of a sense amplifier 120 that is capable of comparing the output of fuse 130 to a reference voltage 122. Sense amplifier 120 provides a data output 126 that is a binary representation of the state of fuse 130. Sense amplifier 120 includes an enable input 124 that is capable of rendering sense amplifier 120 inoperable. In some cases, enable input 124 is used to disable sense amplifier 120 and thereby reduce power dissipation.
Fuse 130 is blown based on a program input 140 that drives a signaling circuit 150. Signaling circuit 150 includes transistors 152, 153, 154, 155, 156, a buffer 157 and a resistor 158 arranged to assure a proper voltage level and timing required to selectably blow fuse 130 upon the desired assertion of program input 140. In particular, when program input 140 is asserted high (i.e., a logic ‘1’), the gate of transistor 154 is asserted low (i.e., a logic ‘0’). This causes the gate of fuse blow transistor 110 to be near VDD (i.e., a logic ‘1’). Asserting the gate of fuse blow transistor 110 at a logic ‘1’ causes a current driven by VPP to traverse fuse 130 and thereby blow fuse 130. Alternatively, when program input 140 is asserted low, the gate of transistor 154 is asserted high. This causes the gate of fuse blow transistor 110 to be near ground (i.e., a logic ‘0’) and fuse 130 is not blown. Transistors 152, 153 assure a delay upon start-up that limits the possibility that fuse 130 will be blown on power-up when program input 140 is unstable. When fuse 130 is completely blown, a voltage near ground (i.e., a logic ‘0’) is asserted at the output of fuse 130 and the input of sense amplifier 120. In contrast, when fuse 130 is not blown, the output of fuse 130 and the input of sense amplifier 120 is asserted as a voltage near VPP (i.e., a logic ‘1’). Data output 126 is a binary representation of the voltage at the output of fuse 130.
While fuse blow circuit 100 is capable of blowing fuse 130 under the proper assertion of program input 140, the process of blowing fuse 130 takes a substantial amount of time. For example, the process of blowing fuse 130 can require in excess of ten milliseconds. Where fuse blow circuit is replicated tens, hundreds or even thousands of times, the length of time required to blow a subset of all of the fuses can become significant lasting many seconds or more. The amount of time spent blowing fuses is both costly and distracting.
Thus, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for utilizing fuse technology.